//控制模块，此模块维护一个全局计数器，根据计数器的值发布相关控制信号
//Last modified by yjq at 2021/5/20
//控制模糊，有待修改。

module control(
    input wire clk,
    input wire rst_n,
    input wire new,
    input wire in_valid,
    input wire w_valid,
    input wire select,
    input wire EN,

    output wire input_W_read,
    output wire W_reg_en,
    output wire hash_reg_en,
    output wire update,//
    output reg bigger16,
    output reg bigger32,
    output reg bigger64,
    //output wire reset,
    output wire[1:0] S1,
    output wire[1:0] S2
);
    reg[67:0] counter;
    reg is_sm3;

    assign reset = new;//冗余。
    /*
    assign W_reg_en = EN & (is_sm3?
    ://sm3
    bigger16|(w_valid));//sha256
    */
    assign update = new|(is_sm3?counter[67]:counter[63]);

    always@(posedge clk or negedge rst_n)begin
        if(!rst_n)begin
            counter<=67'b1;
        end else begin
            if(update)begin
                counter<=67'b1;
            end else if(w_valid)begin
                counter<={{counter[66:0]},1'b1};
            end else if(bigger16) begin
                counter<={{counter[66:0]},1'b1};
            end
        end
    end 

    always@(posedge clk or negedge rst_n)begin
        if(!rst_n)begin
            bigger16<=1'b0;
        end else begin
            if(counter[15]==1'b1/* (counter[15]==1'b1)&w_valid */)begin
                bigger16<=1'b1;
            end else if(update)begin
                bigger16<=1'b0;
            end
        end
    end

    always@(posedge clk or negedge rst_n)begin
        if(!rst_n)begin
            bigger32<=1'b0;
        end else begin
            if(counter[31]==1'b1)begin
                bigger32<=1'b1;
            end else if(update)begin
                bigger32<=1'b0;
            end
        end
    end

    always@(posedge clk or negedge rst_n)begin
        if(!rst_n)begin
            bigger64<=1'b0;
        end else begin
            if(counter[63]==1'b1)begin
                bigger64<=1'b1;
            end else if(update)begin
                bigger64<=1'b0;
            end
        end
    end


endmodule
